RISCV Processor based Computer Architecture RISCV Processor based Computer Architecture
 

1  Introduction to computer architecture: (download)

  • Computer Abstractions,
  • Understanding Software and Hardware interface

2  Importance of Open Processor:  (download)

  • Basic Component of Processor Architectures
  • ALU, Registers, Control, Data and Address Bus, ISA, Program and Data Memory

3  Processor Architectures:  (download)

  • Single Cycle
  • Pipe-lined, Multi-Cycle
  • Out-of-Order and Super-scalar

4  Data and Control Path of RISC-V ISA 

  • Pipeline Processor Architecture
  • Data and Control Hazards
  • Advanced and Complex Instructions Sets and Integration in Processor

5  Programming Processor using Assembly and C Language  (download)

  • Arithmetic, Logic,
  • Read/Write and Branch Instructions

6  Memory Hierarchy Design, SRAM, DRAM, Cache Memories, Types of  caches  (download)


7  Cache Architecture and Memory Interfacing  (download)


9  Memory Mapping and Input Output Addressing Scheme   (download)


10  Memory Management Unit and Virtual Memory   (download)


11  System on a Chip Architecture  (download)


12  Different types of Computer Architectures  (download)


13  Programming Computer Architectures  (download)

  • C/C++,
  • Compilers
  • Operating Systems

14  Single Core and Multi-core Programming  (download)


15  Parallel Processing Multi-Tasking and Multi-Threading  (download)

UCERD Rawalpindi
Supercomputing Center
UCERD Murree
Computer Architecture (RISCV Processor Based)
This course explores the principles of computer architecture through the RISC-V instruction set. Students will learn about instruction set design, performance optimizations, and modern multi-core and memory hierarchy techniques specific to RISC-V systems. The course equips students with the skills to understand and develop open hardware system on chip computer architecture, optimize applications and address computationally intensive problems using the RISC-V ISA.
Learning Outcomes:
1. Describe the performance of different Processor Architectures and how design trade-off  improves performance.
2. Analyze the data-path and control of single-cycle and Multi-cycle architecture, and performance enhancement by pipelining using open-source compilers, simulators and emulators.
3. Design a Processor System on Chip architecture having cache and main memory unit.
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Unal Center of Educaiton Research & Development