Field Programable Gate Arrays based System Design
FPGAs typically run at much slower clock speeds than the latest CPUs, yet they can more than make up for this with their superior memory bandwidth, high degree of parallelization, and the customization that is possible. There is currently a tremendous amount of attention in FPGAs.
If we compare the cost of creating an FPGA design, it is much lower than that for an ASIC or ASSP. At the same time, implementing design changes is much easier in FPGAs and the time-to-market for such designs is much faster.

Digital designs once built in custom silicon are increasingly implemented in field programmable gate arrays (FPGAs). Effective FPGA system design requires a strong understanding of design issues and constraints, and an understanding of the latest FPGA-specific techniques.
At the end of the course student can understand the FPGA based system design, solve a real-world problems and map and port these problems in an FPGA board.

Students Get Hands-On Experience of State of the art tools and technologies

1) FPGA Architecture and Implementation
2) System Design using 65 nm and 28 nm FPGA technology
3) Hardware Design Methodology  - Register Transfer Level Design using VHDL/Verilog
4) Static Timing and Power Analysis
5) Simulation on modelsim
6) EDA Tool flow: (Xilinx Vivado, Altera Quartus, Syplicity Tool)
7) System on Chip (Zynq-7000 line of 28 nm SoC devices and Altera DE1 Soc dual-core Cortex-A9)
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Past Present and Future of Integrated Circuits
Fundamental Concepts I
Fusible link technologies
Anti-fuse technologies
EPROM-based technologies
Fundamental Concepts II
FLASH-based technologies
SRAM - based Technologies
Permanently Programmed Gate Array
FPGA and VLSI
Fundamentals of Hardware Description Languages (HDL), Verilog, VHDL
Design Entity
Code Structure
Data Types
Operands
Operators
Design For Test
Testing, Simulating and Prototyping
Basic Components of Digital System Design
Memories (SRAMs, DRAMs)
Microprocessors
Buses
Gate Level Design
Combinational Logic Circuits
Adder, Multiplier Design
RTL (Register Transfer Level Design)
Sequential Circuit
Multiplexer, Encoder, Decoder,  State Machine, Orbiter and Scheduler
Finite State Machine with Data Path
System Architecture Design
ALU  (Adder, Multiplier Single Precision, Double Precision)
Memories (SDRAM, DRAM)
Buses
System Architecture Design
Abstract Level Design
Tools:  ROCCC, C2HDL LEGUP, Vivado, Quartus, Modelsim
Components: ALU, Buses, Registers etc.
System on Chip Design
Using processors, caches, buses etc.
Multi-core System on Chip Design
Past Present and Future of Integrated Circuits
 
 
 
Dr. Tassadaq Hussain.

He is a permanent faculty member at, Riphah International University.
He did his Ph.D. from Barcelona-tech Spain, in collaboration with Barcelona Supercomputing Center and Microsoft Research Center.

He is a member of HiPEAC: European Network on High Performance and Embedded Architecture and Compilation, Barcelona Supercomputing Center and Microsoft ResearchCentre Spain.
Until January 2018, he had more than 14 years of industrial experience including, Barcelona Supercomputing Centre Spain, Infineon technology France, Microsoft Research Cambridge, PLDA Italia, IBM Zurich Switzerland, and REPSOL Spain. He has published more than 50 international publications and filed 5 patents.

Tassadaq's main research lines are Machine Learning, Parallel Programming, Heterogeneous Multi-core Architectures, Single board Computers, Embedded Computer Vision, Runtime Resource Aware Architectures, Software Defined Radio and Supercomputing for Artificial Intelligence and Scientific Computing.

www.tassadaq.ucerd.com
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